My name is Deepak Siddharth Parthipan.

Here I would like to self-journal concepts and problems as I learn, thought process, projects and other self growth hacks. Learning is a life-long process.

I am very passionate about Hardware design and verification. Im interested in exploring below subjects but not limited to.

Design: Logic Design, Algorithms, Comp Arch, Embedded, Signal Processing.
Hardware Verification: DV architecture, UVM, Assertions, Formal, GLS.
Language/OS: System Verilog, C++, Python, ASM, Unix, Simulink(MATLAB).

I also like learning about how to develop meta learning skills, read blogs about mental models, cognitive psychology, productivity. If you land at this page do hit me up, I would love to hear from you.