Static vs Automatic
In short what is static and automatic in system verilog.
| Static | Automatic | |
|---|---|---|
| Memory | Permanant(BSS, DATA). | Temporary(Stack). |
| Life-time | Throughout the simulation. | Until the method finishes. |
| Variables | Module & Program | Class |
| Methods | Module | Class |
STATIC
- By default all function/variable inside a module is static, unless declared automatic.
- If a function as automatic, all the variables inside the function will be automatic, unless a specific variable is declared as static.
- Although by default functions are static, you can specifically declare it as static and required variables as automatic.
AUTOMATIC
- By default all function/variable inside a class is automatic, unless declared static.
- If a function as static, all the variables inside the function will be static, unless a specific variable is declared as automatic.